1. Field of the Invention
The present invention relates to a semiconductor package and, more particularly, to a stacked semiconductor package and a method for assembling the same.
2. Discussion of the Related Art
Semiconductor package is classified into inline package and outline package. DIP (dual inline package), SIP (single inline package), and PGA (pin grid array) belong to the inline package where pins are inserted into holes formed on print wire plates without package lead and are soldered. DIP and SIP are of a lead frame type and PGA is of a pin type.
As for outline package, holes are unnecessary. It is mounted on one surface or both surfaces of an IC wire plate. This kind of package is very light and simple and the packaging density of a wire plate is much enhanced. Individual packages such as SOP (small outline package), TSOP (thin small outline package), SOJ (small outline J-bend), and TQFP (thin quad flat package) belong to the outline package.
As for system package, there are TAB (tape automated bonding), C-4, Bear chips, and so forth.
FIG. 1 shows comparisons of various kinds of packages in forms, sizes, heights and so on. FIG. 2 is an example of a multi chip module.
As shown in FIGS. 1 and 2, all packages have very big sizes. Besides, it is necessary to assemble individually-packaged chips. In other words, though chips having diverse functions are integrated in packages with the MCM (multi chip module) method, many process steps of installing chips on a ceramic substrate, which it is difficult to fabricate, and possibility of generation of failures is high. Moreover, when a failure is generated, it is difficult to find out which chip has the failure. Thus, to prevent such a problem, packaged chips are installed on a ceramic substrate. As a result, unnecessary process steps are added and the production cost is increased, though.
The background semiconductor package has the following problems. Since individual chips should be assembled, the external sizes of the chips are very big. Further, since packaged chips are installed on a ceramic substrate, the process becomes complicated and the possibility of generation of failures becomes heightened, and the production cost becomes expensive. Furthermore, it is hard to diverge and repair when failures are generated.